⚡ Quick Summary
- RISC-V builds take 143 minutes vs 36 minutes for ARM on the same Fedora package — roughly a 4x performance gap
- Current RISC-V cores comparable to ARM's lowest-power Cortex-A55 efficiency tier
- Fedora RISC-V port runs with LTO disabled to manage memory and build time constraints
- Upcoming hardware may improve but RISC-V needs approximately 3x improvement for baseline viability
What Happened
A veteran Linux developer working on the Fedora RISC-V port has published detailed benchmarks exposing the severe performance gap between current RISC-V hardware and established architectures. Marcin Juszkiewicz, who has spent three months porting Fedora Linux to RISC-V, documented that building the same software packages takes roughly four times longer on RISC-V compared to ARM — with some builds pushing even worse ratios when accounting for memory constraints and disabled optimizations.
In a detailed blog post, Juszkiewicz compared build times for the binutils package across all Fedora-supported architectures. The results were stark: the aarch64 (ARM) build completed in 36 minutes on 12 cores with 46 GB RAM, while the riscv64 build took 143 minutes on 8 cores with just 16 GB RAM. Even accounting for the core count difference, RISC-V's per-core performance lagged dramatically. The x86_64 build finished in 29 minutes, and even the relatively niche s390x mainframe architecture managed 37 minutes.
Making matters worse, the Fedora RISC-V port currently builds with Link-Time Optimization (LTO) disabled to reduce memory usage and build times — meaning the actual performance of RISC-V compiled binaries may be worse than they would be with full optimization enabled.
Background and Context
RISC-V has been positioned as the future of open-source chip architecture — a free, open instruction set that could break the dominance of ARM in mobile and embedded computing and x86 in servers and desktops. Billions of dollars have flowed into RISC-V startups and development, with major companies including Google, Qualcomm, and Samsung joining the RISC-V International consortium. The promise is compelling: an architecture that anyone can implement without licensing fees, fostering innovation and competition.
However, the reality of RISC-V hardware in 2026 is that it remains firmly in the early adopter phase. Current RISC-V builders for Fedora use four or eight core systems with 8 to 32 GB of RAM, featuring cores commonly compared to ARM Cortex-A55 — the lowest-power cores in contemporary ARM chip designs. This is not a comparison against ARM's high-performance Cortex-X series cores; RISC-V is being benchmarked against ARM's efficiency-tier silicon and still losing substantially.
Juszkiewicz's work involved triaging the Fedora RISC-V tracker, submitting 86 pull requests to fix package build issues, and working through the painstaking process of getting a major Linux distribution running reliably on a nascent architecture — the kind of unglamorous engineering work that determines whether a technology transitions from promise to reality.
Why This Matters
The performance data matters because it provides a concrete, real-world assessment of where RISC-V actually stands versus the marketing narratives that have surrounded it. While RISC-V proponents often point to the architecture's theoretical advantages — extensibility, no licensing fees, growing ecosystem — enterprises and developers making hardware procurement decisions need to understand the current practical reality.
For data centers and cloud providers evaluating RISC-V as an alternative to ARM or x86 servers, a 4x performance penalty on compilation workloads — a reasonable proxy for general computational throughput — represents a significant barrier. Organizations that manage their IT infrastructure with an affordable Microsoft Office licence and standard enterprise tools need architectures that deliver competitive performance today, not just architectural elegance tomorrow.
Industry Impact
The RISC-V ecosystem has several promising developments on the horizon that could narrow the performance gap. Juszkiewicz specifically mentioned the UltraRISC UR-DP1000 SoC on the Milk-V Titan motherboard and SpacemiT K3-based systems as upcoming improvements, though he characterized them as incremental rather than transformative. His benchmark for viability: RISC-V needs hardware capable of building binutils in under one hour with LTO enabled and system-wide optimizations — roughly a 3x improvement from current hardware.
The infrastructure requirements are also significant. RISC-V builders need to be rackable and remotely manageable — basic requirements for data center deployment that current RISC-V hardware often doesn't meet. This matters for enterprise environments where professionals use a genuine Windows 11 key and expect their infrastructure to meet enterprise-grade manageability standards.
Expert Perspective
Architecture analysts have emphasized that RISC-V's current performance is not necessarily indicative of the architecture's ceiling. ARM's own journey from low-power mobile cores to the data-center-capable Neoverse series took over a decade of sustained investment and iteration. RISC-V is earlier in that curve, and significant performance improvements are expected as more silicon design talent and investment flows into high-performance RISC-V core development.
However, others caution that RISC-V faces a bootstrapping problem: software ecosystem maturity requires hardware performance, but hardware investment requires software ecosystem demand. Fedora's porting effort is precisely the kind of work needed to break this cycle, even if the current performance numbers are sobering.
What This Means for Businesses
For businesses evaluating their long-term hardware strategy, the RISC-V performance data suggests a "watch but wait" posture. The architecture's open nature and growing ecosystem make it a credible long-term alternative, but current hardware is not ready for production workloads outside specialized embedded applications. Companies investing in enterprise productivity software should continue building on established ARM and x86 platforms while tracking RISC-V's progress for future opportunities.
Key Takeaways
- RISC-V builds take roughly 4x longer than ARM for the same packages in Fedora Linux
- Current RISC-V cores are comparable to ARM's lowest-power Cortex-A55 — the efficiency tier, not the performance tier
- Fedora's RISC-V port runs with LTO disabled to manage memory and build time constraints
- 86 package patches were needed to get Fedora building on RISC-V
- Upcoming hardware like UltraRISC UR-DP1000 may improve the situation but won't close the gap entirely
- RISC-V needs approximately 3x improvement in hardware performance to reach baseline viability
Looking Ahead
The next 18-24 months will be critical for RISC-V's trajectory. New silicon designs from companies like SiFive, Ventana Micro, and Tenstorrent promise significant performance improvements, while the growing software ecosystem — exemplified by Fedora's porting effort — will make RISC-V increasingly practical for evaluation. The open architecture's long-term potential remains real, but the path from "promising" to "competitive" is measured in years of sustained engineering work.
Frequently Asked Questions
How much slower is RISC-V compared to ARM?
In Fedora Linux package builds, RISC-V takes roughly 4x longer than ARM (143 minutes vs 36 minutes for binutils), with the gap potentially wider for more complex packages.
Is RISC-V ready for enterprise use?
Not for general-purpose computing workloads. Current RISC-V hardware is suitable for evaluation and specialized embedded applications, but significant performance improvements are needed before it can compete with ARM or x86 in production environments.
When will RISC-V close the performance gap?
Industry analysts estimate 18-24 months before significantly faster RISC-V silicon arrives from companies like SiFive and Ventana Micro, with full competitiveness likely taking several more years of sustained development.